1. Field of the Invention
This invention generally relates to system-on-chip (SoC) off-SoC memory management and, more particularly, to a system and method for using a SoC hardware core to control the frequency of memory operations.
2. Description of the Related Art
As noted in Wikipedia, a memory controller is a digital circuit that manages the flow of data going to and from the main memory. The memory controller can be a separate chip or integrated into another chip, such as on the die of a microprocessor. Computers using Intel microprocessors have conventionally had a memory controller implemented on their motherboard's Northbridge, but some modern microprocessors, such as DEC/Compaq's Alpha 21364, AMD's Athlon 64 and Opteron processors, IBM's POWER5, Sun Microsystems UltraSPARC T1, and more recently, Intel Core i7 have a memory controller on the microprocessor die to reduce the memory latency. While this arrangement has the potential of increasing system performance, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated Northbridge.
The integration of the memory controller onto the die of the microprocessor is not a new concept. Some microprocessors in the 1990s such as the DEC Alpha 21066 and HP PA-7300LC had integrated memory controllers, but to reduce the cost of systems by removing the requirement for an external memory controller instead of increasing performance.
Memory controllers contain the logic necessary to read and write dynamic random access memory (DRAM), and to “refresh” the DRAM by sending current through the entire device. Without constant refreshes, DRAM loses the data written to it as the capacitors leak their charge within a fraction of a second (not less than 64 milliseconds according to JEDEC standards).
Reading and writing to DRAM is facilitated by use of multiplexers and demultiplexers, by selecting the correct row and column address as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM can select the correct memory location and return the data (once again passed through a multiplexer to reduce the number of wires necessary to assemble the system).
Bus width is the number of parallel lines available to communicate with the memory cell. Memory controller bus widths range from 8-bit in earlier systems, to 512-bit in more complicated systems and video cards. Double data rate (DDR) memory controllers are used to drive DDR SDRAM, where data is transferred on the rising and falling access of the memory clock of the system. DDR memory controllers are significantly more complicated than Single Data Rate controllers, but allow for twice the data to be transferred without increasing the clock rate or increasing the bus width to the memory cell.
Dual Channel memory controllers are memory controllers where the DRAM devices are separated onto two different buses, allowing two memory controllers to access them in parallel. This dual arrangement doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, line capacitance, and the need for parallel access lines to have identical lengths, more channels are very difficult to add.
Fully buffered memory systems place a memory buffer device on every memory module (called an FB-DIMM when Fully Buffered RAM is used), which unlike conventional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory location). This latency increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
Regardless of whether the memory control is a separate device or embedded with the microprocessor, memory parameters are conventionally set at power on, and cannot be changed during operation. Changing memory parameters while the system is running requires many factors to be taken into account and, requires specialized logic that adds to the cost of the chips. Given that low cost is a key selling factor, and that battery life and power efficiency are less so, means that such functionality has not been addressed before.
Changing the memory hardware timing on-the-fly can lead to complications, such as memory corruption, microprocessor hang ups due to glitches and loss of state. Typically, such an operation would require the impacted cores be temporarily halted, VCO frequencies to be changed, and interfaces to be recalibrated. None of these tasks are trivial. These tasks are typically performed at power-on because there are no applications running at that time.
It would be advantageous if memory access speeds could be changed on-the-fly using a memory speed control core (hardware block) in a SoC.